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XA2C32A CoolRunner-II Automotive CPLD
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DS552 (v1.1) May 5, 2007
Product Specification
Features
* AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade Guaranteed to meet full electrical specifications over TA = -40 C to +105 C with TJ Maximum = +125 C (Q-grade) Optimized for 1.8V systems Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation: 1.5V through 3.3V Available in Pb-free 44-pin VQFP with 33 user I/O Advanced system features - Fastest in system programming * 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Two separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes * Optional DualEDGE triggered registers - Global signal options with macrocell control * Multiple global clocks with phase selection per macrocell * Multiple global output enables * Global set/reset - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional configurable grounds on unused I/Os - Optional bus-hold, 3-state or weak pullup on selected I/O pins - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels - PLA architecture * Superior pinout retention * 100% product term routability across function block - Hot pluggable
Description
The CoolRunnerTM-II Automotive 32-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. The CoolRunner-II Automotive 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II Automotive 32-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
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Refer to the CoolRunnerTM-II Automotive CPLD family data sheet for architecture description. WARNING: Programming temperature range of TA = 0 C to +70 C
(c) 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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XA2C32A CoolRunner-II Automotive CPLD
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RealDigital Design Technology
Xilinx CoolRunner-II Automotive CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II Automotive CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II Automotive CPLDs achieve both high performance and low power operation.
is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II Automotive CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XA2C32A IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15(1) Output VCCIO 3.3 3.3 2.5 1.8 1.5 Input VCCIO 3.3 3.3 2.5 1.8 1.5
Supported I/O Standards
The CoolRunner-II Automotive 32-macrocell device features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard
(1) LVCMOS15 requires Schmitt-trigger inputs.
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ICC (mA)
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0 0 50 100 150 200
DS552_01_092006
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical ICC (mA) 0.016 25 0.87 50 1.75 75 2.61 100 3.44 150 5.16 175 5.99 200 6.81
Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block).
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XA2C32A CoolRunner-II Automotive CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VJTAG VIN
(2)
Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground Voltage applied to 3-state output Storage Temperature (ambient) Junction Temperature
Value -0.5 to 2.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -65 to +150 +125
Units V V V V V V C C
VCCAUX
(1)
VTS(1) TSTG(3) TJ
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to -2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427.
Recommended Operating Conditions
Symbol VCC Parameter Supply voltage for internal logic and input buffers Industrial TA = -40C to +85C Q-Grade TA = -40C to +105C, TJ Maximum = +125C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V
VCCIO
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VCCAUX
JTAG programming pins
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB ICC
(1)
Parameter Standby current Industrial Standby current Q-grade Dynamic current JTAG input capacitance Global clock input capacitance I/O capacitance Input leakage current I/O High-Z leakage
Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V
Typical 38 38 -
Max. 150 550 1.0 4.0 10 12 10 +/-10 +/-10
Units A A mA mA pF pF pF A A
CJTAG CCLK CIO IIL(2) IIH
Notes: 1. 16-bit up/down resettable binary counter (one per Function Block) tested at VCC = VCCIO = 1.9V
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LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage, Industrial grade High level output voltage, Q-grade VOL Low level output voltage, Industrial grade Low level output voltage, Q-grade IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V IOH = -4 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V IOL = 4 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Test Conditions Min. 3.0 2 -0.3 VCCIO - 0.4V VCCIO - 0.2V VCCIO - 0.4V VCCIO - 0.2V Max. 3.6 3.9 0.8 0.4 0.2 0.4 0.2 Units V V V V V V V V V V V
LVCMOS 2.5V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage, Industrial grade High level output voltage, Q-grade VOL Low level output voltage, Industrial grade Low level output voltage, Q-grade IOH = -8 mA, VCCIO = 2.3V IOH = -0.1 mA, VCCIO = 2.3V IOH = -4 mA, VCCIO = 2.3V IOH = -0.1 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V IOL = 0.1mA, VCCIO = 2.3V IOL = 4 mA, VCCIO = 2.3V IOL = 0.1mA, VCCIO = 2.3V
1.
Test Conditions
Min. 2.3 1.7 -0.3 VCCIO - 0.4V VCCIO - 0.2V VCCIO - 0.4V VCCIO - 0.2V -
Max. 2.7
VCCIO
Units V V V V V V V V V V V
+ 0.3(1) -
0.7
0.4 0.2 0.4 0.2
The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.
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XA2C32A CoolRunner-II Automotive CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage, Industrial grade High level output voltage, Q-grade VOL Low level output voltage, Industrial grade Low level output voltage, Q-grade IOH = -8 mA, VCCIO = 1.7V IOH = -0.1 mA, VCCIO = 1.7V IOH = -4 mA, VCCIO = 1.7V IOH = -0.1 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V IOL = 4 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V Test Conditions Min. 1.7 0.65 x VCCIO -0.3 VCCIO - 0.45 VCCIO - 0.2 VCCIO - 0.45 VCCIO - 0.2 Max. 1.9
VCCIO
Units V V V V V V V V V V V
+ 0.3(1) -
0.35 x VCCIO
0.45 0.2 0.45 0.2
1. The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.
LVCMOS 1.5V DC Voltage Specifications(1)
Symbol VCCIO VT+ VTVOH High level output voltage, Industrial grade High level output voltage, Q-grade VOL Low level output voltage, Industrial grade Low level output voltage, Q-grade
Notes: 1. Hysteresis used on 1.5V inputs.
Parameter Input source voltage Input hysteresis threshold voltage
Test Conditions
Min. 1.4 0.5 x VCCIO 0.2 x VCCIO
Max. 1.6 0.8 x VCCIO 0.5 x VCCIO 0.4 0.2 0.4 0.2
Units V V V V V V V V V V V
IOH = -8 mA, VCCIO = 1.4V IOH = -0.1 mA, VCCIO = 1.4V IOH = -4 mA, VCCIO = 1.4V IOH = -0.1 mA, VCCIO = 1.4V IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V IOL = 4 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V
VCCIO - 0.45 VCCIO - 0.2 VCCIO - 0.45 VCCIO - 0.2 -
Schmitt Trigger Input DC Voltage Specifications
Symbol VCCIO VT+ VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 3.9 0.8 x VCCIO 0.5 x VCCIO Units V V V
AC Electrical Characteristics Over Recommended Operating Conditions
-6 Symbol TPD1 TPD2 TSUD Parameter Propagation delay single p-term Propagation delay OR array Direct input register clock setup time Min. 2.2 Max. 5.5 6.0 2.2 Min. -7 Max. 5.5 6.0 Units ns ns ns
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XA2C32A CoolRunner-II Automotive CPLD -6 Symbol TSU1 TSU2 THD TH TCO FTOGGLE
(1) (2) (2)
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-7 Max. 4.7 300 200 182 137 128 6.0 5.5 6.7 6.9 6.8 5.5 50 Min. 2.6 3.1 0.0 0.0 0.9 1.3 1.8 1.6 1.2 3.0 0.0 2.2 6.0 6.0 Max. 4.7 300 200 182 137 128 6.0 6.2 8.0 7.6 6.8 5.5 50 Units ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Parameter Setup time fast (single p-term) Setup time (OR array) Direct input register hold time P-term hold time Clock to output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Direct input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Asynchronous preset/reset pulse width (High or Low)
Min. 2.6 3.1 0.0 0.0 0.9 1.3 1.8 1.6 1.2 3.0 0.0 2.2 6.0 6.0 -
FSYSTEM1 FSYSTEM2 FEXT1(3) FEXT2
(3)
TPSUD TPSU1 TPSU2 TPHD TPH TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TPCW TAPRPW TCONFIG
(4)
Configuration time
Notes: 1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II Automotive CPLD family data sheet). 2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while FSYSTEM2 is through the OR array. 3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array. 4. Typical configuration current during TCONFIG is 500 A.
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XA2C32A CoolRunner-II Automotive CPLD
Internal Timing Parameters
-6 Symbol Buffer Delays TIN TDIN TGCK TGSR TGTS TOUT TEN P-term Delays TCT TLOGI1 Parameter(1) Input buffer delay Direct register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single p-term delay adder Min. 1.8 0.0 1.7 0.0 Max. 1.7 2.4 2.0 2.0 2.1 2.0 3.4 1.6 1.1 0.5 0.7 2.5 0.7 1.5 1.4 0.8 4.0 1.0 5.0 4.0 0.0 5.0 Min. 1.8 0.0 1.7 0.0 -7 Max. 1.7 2.4 2.0 2.0 1.5 2.0 4.7 1.6 1.1 0.5 0.7 2.5 0.7 1.5 1.4 0.2 4.2 1.0 5.0 4.0 0.0 5.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TLOGI2 Multiple p-term delay adder Macrocell Delay TPDI Input to output valid TLDI TSUI THI TECSU TECHO TCOI TAOI
Feedback Delays
Setup before clock (transparent latch) Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Feedback delay Macrocell to global OE delay Hysteresis input adder Output adder Output slew rate adder Hysteresis input adder Output adder Output slew rate adder
TF TOEM THYS15 TOUT15 TSLEW15 THYS18 TOUT18 TSLEW
I/O Standard Time Adder Delays 1.5V CMOS
I/O Standard Time Adder Delays 1.8V CMOS
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Internal Timing Parameters (Continued)
-6 Symbol TIN25 THYS25 TOUT25 Parameter(1) Standard input adder Hysteresis input adder Output adder Min. Max. 0.6 4.0 0.7 5.0 0.6 4.0 1.2 5.0 Min. I/O Standard Time Adder Delays 2.5V CMOS
-7 Max. 0.7 4.0 0.8 5.5 0.8 4.0 1.2 6.6 Units ns ns ns ns ns ns ns ns
TSLEW25 Output slew rate adder I/O Standard Time Adder Delays 3.3V CMOS/TTL TIN33 Standard input adder THYS33 TOUT33 TSLEW33 Hysteresis input adder Output adder Output slew rate adder
Notes: 1. 1.5 ns input pin signal rise/fall.
Switching Characteristics
VCC = VCCIO = 1.8V @ 25oC
5.5
AC Test Circuit
VCC R1
5.0
Device Under Test R2 CL
Test Point
4.5
TPD2 (ns)
4.0
Output Type
3.5
R1 268 275 188 112.5 150
R2 235 275 188 112.5 150
CL 35 pF 35 pF 35pF 35pF 35pF
LVTTL33 LVCMOS33 LVCMOS25
1 2 4 8 16
3.0
LVCMOS18 LVCMOS15
Number of Outputs Switching
DS091_02_112002
CL includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs.
DS_ACT_08_14_02
Figure 2: Derating Curve for TPD
Figure 3: AC Load Circuit
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XA2C32A CoolRunner-II Automotive CPLD
Typical I/O Output Curves
3.3V
60
50
IO (Output Current mA)
40 1.8V 30
2.5V
Iol
20 1.5V 10
0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5
VO (Output Volts)
XC32_VoIo_all_0403
Figure 4: Typical I/V Curve for XA2C32A
Pin Descriptions
Function Block 1 1 1 1(GTS1) 1(GTS0) 1(GTS3) 1(GTS2) 1(GSR) 1 1 1 1 1 1 1 1 2 2 2 2 2(GCK0) 2(GCK1) 2(GCK2) Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 VQG44 38 37 36 34 33 32 31 30 29 28 27 23 22 21 20 19 39 40 41 42 43 44 1 I/O Bank Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1
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Pin Descriptions (Continued)
Function Block 2 2 2 2 2 2 2 2 2 Macrocell 8 9 10 11 12 13 14 15 16 VQG44 2 3 5 6 8 12 13 14 16 I/O Bank Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1
Notes: 1. GTS = global output enable, GSR = global set reset, GCK = global clock 2. GTS, GSR, and GCK pins can also be used for general purpose I/O.
XA2C32A Global, JTAG, Power/Ground and No Connect Pins
Pin Type TCK TDI TDO TMS Input Only VCCAUX (JTAG supply voltage) Power internal (VCC) Power bank 1 I/O (VCCIO1) Power bank 2 I/O (VCCIO2) Ground No connects Total user I/O (includes dual function pins)
Notes: 1. All packages pin compatible with larger macrocell densities
VQG44(1) 11 9 24 10 18 (bank 2) 35 15 7 26 4,17,25 33
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XA2C32A CoolRunner-II Automotive CPLD
Ordering Information
Part Number XA2C32A-6VQG44I XA2C32A-7VQG44Q Pin/Ball Spacing 0.8mm JA (C/Watt) 47.7 JC (C/Watt) 8.2 Package Type Very Thin Quad Flat Pack; Pb-free Package Body Dimensions 10mm x 10mm Ind. (I)(1) I/O 33 Hi-T(Q) I Q
Notes: 1. I = Industrial (TA = -40C to +85C); Q = Automotive (TA = -40C to +105C with TJ Maximum = +125C)
Pb-Free Example: XA2C32A Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range
-6 VQ
G
44
I
Device Part Marking
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Device Type Package Speed Operating Range
XA2Cxxx VQG44 6I
This line not related to device part number
Part marking for non-chip scale package
Figure 5: Sample Package with Part Marking
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44 43 42 41 40 39 38 37 36 35 34
I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O I/O VAUX I/O(1)
I/O(2) I/O I/O GND I/O I/O VCCIO1 I/O TDI TMS TCK
CoolRunner-II Automotive Requirements and Recommendations
Requirements
The following requirements are for all automotive applications: 1. Use a monotonic, fast ramp power supply to power up CoolRunner-II . A VCC ramp time of less than 1 ms is required. 2. Do not float I/O pins during device operation. Floating I/O pins can increase ICC as input buffers will draw 1-2 mA per floating input. In addition, when I/O pins are floated, noise can propagate to the center of the CPLD. I/O pins should be appropriately terminated with bus-hold or pull-up. Unused I/Os can also be configured as CGND (programmable GND). 3. Do not drive I/O pins without VCC/VCCIO powered. 4. Sink current when driving LEDs. Because all Xilinx CPLDs have N-channel pull-down transistors on outputs, it is required that an LED anode is sourced through a resistor externally to VCC. Consequently, this will give the brightest solution. 5. Avoid pull-down resistors. Always use external pull-up resistors if external termination is required. This is because the CoolRunner-II Automotive CPLD, which includes some I/O driving circuits beyond the input and output buffers, may have contention with external pull-down resistors, and, consequently, the I/O will not switch as expected. 6. Do not drive I/Os pins above the VCCIO assigned to its I/O bank. a. The current flow can go into VCCIO and affect a user voltage regulator. b. It can also increase undesired leakage current associated with the device. c. If done for too long, it can reduce the life of the device.
I/O I/O I/O VCC I/O GND I I/O I/O I/O I/O
12 13 14 15 16 17 18 19 20 21 22
1 2 3 4 5 6 7 8 9 10 11
VQG44 Top View
33 32 31 30 29 28 27 26 25 24 23
I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O I/O VCCIO2 GND TDO I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset
Figure 6: VQ44 Package
7. Do not rely on the I/O states before the CPLD configures. During power up, the CPLD I/Os may be affected by internal or external signals. 8. Use a voltage regulator which can provide sufficient current during device power up. As a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a CPLD in order to guarantee the CPLD can configure successfully. 9. Ensure external JTAG terminations for TMS, TCK, TDI, TDO should comply with the IEEE 1149.1. All Xilinx CPLDs have internal weak pull-ups on TDI, TMS, and TCK.
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XA2C32A CoolRunner-II Automotive CPLD 4. Do not disregard report file warnings. Software identifies potential problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. Understand the Timing Report. This report file provides a speed summary along with warnings. Read the timing file (*.tim) carefully. Analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. Review Fitter Report equations. Equations can be shown in ABEL-like format, or can also be displayed in Verilog or VHDL formats. The Fitter Report also includes switch settings that are very informative of other device behaviors. 7. Let design software define pinouts if possible. Xilinx CPLD software works best when it selects the I/O pins and manages resources for users. It can spread signals around and improve pin-locking. If users must define pins, plan resources in advance. 8. Perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. Distribute SSOs (Simultaneously Switching Outputs) evenly around the CPLD to reduce switching noise. 10. Terminate high speed outputs to eliminate noise caused by very fast rising/falling edges.
10. Attach all CPLD VCC and GND pins in order to have necessary power and ground supplies around the CPLD. 11. Decouple all VCC and VCCIO pins with capacitors of 0.01 F and 0.1 F closest to the pins for each VCC/VCCIO-GND pair. 12. Configure I/Os properly. CoolRunner-II Automotive CPLDs have I/O banks; therefore, signals must be assigned to appropriate banks (LVCMOS33, LVCMOS18 ...)
Recommendations
The following recommendations are for all automotive applications. 1. Use strict synchronous design (only one clocking event) if possible. A synchronous system is more robust than an asynchronous one. 2. Include JTAG stakes on the PCB. JTAG stakes can be used to test the part on the PCB. They add benefit in reprogramming part on the PCB, inspecting chip internals with INTEST, identifying stuck pins, and inspecting programming patterns (if not secured). 3. CoolRunner-II Automotive CPLDs work with any power sequence, but it is preferable to power the VCCI (internal VCC) before the VCCIO for the applications in which any glitches from device I/Os are unwanted.
Automotive Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
Additional Information
Additional information is available for the following CoolRunner-II topics: * * * * * * * XAPP784: Bulletproof CPLD Design Practices XAPP375: Timing Model XAPP376: Logic Engine XAPP378: Advanced Features XAPP382: I/O Characteristics XAPP389: Powering CoolRunner-II XAPP399: Assigning VREF Pins To access these and all application notes with their associated reference designs, click the following link and scroll down the page until you find the document you want: CoolRunner-II Data Sheets and Application Notes Device Packages
DS552 (v1.1) May 5, 2007 Product Specification
www.xilinx.com
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XA2C32A CoolRunner-II Automotive CPLD
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Revision History
The following table shows the revision history for this document. Date 10/31/06 05/05/07 Version 1.0 1.1 Initial Xilinx release. Change to VIH specification for 3.3V, 2.5V and 1.8V LVCMOS. Revision
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www.xilinx.com
DS552 (v1.1) May 5, 2007 Product Specification

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